Camera Ready Manuscript Submission - Electronics and Communications

List of Accepted Papers

The list of accepted papers is appended at the end of this page

Please note:

· The full paper will be the paper of 6 pages as per IEEE conference paper template, and the presentation time for full paper will be 30 minutes.

· The short paper will be the paper of 4 pages as per IEEE conference paper template, and the presentation time for short paper will be 20 minutes.

· The industry forum paper is for presentation only with presentation time of 30 minutes. This paper will not be forwarded to IEEE for inclusion in conference proceedings on IEEE explore.

· The registrations are open, please visit: Registration

For CRC preparations follow the below mentioned instructions.

Please read the following instructions carefully before submitting final manuscript.

· All the accepted papers must be in the IEEE proceedings two-column format (A4 size). You can find the templates provided by IEEE here.

· The maximum length of the camera-ready manuscript must be 6 pages including figures, tables, and references.

· Papers exceeding the page limits will not be accepted.

· The deadline for camera ready manuscript and copyright form submission is 15^th November 2024.

Paper Submission Instructions

Step-1 Revised final manuscript

· Please address all the reviewer’s comments in the final camera-ready manuscript.

· Please make sure that all figures are high quality.

· Please don’t use author titles (Dr., Mr., etc.) in front of names.

· Remove all headers and footers including page numbering.

Step-2 Add Title and copyright notice

· Add the below title of the Conference as a header on the 1st page of the camera-ready manuscript.

The 33^rd Asian Test Symposium (ATS 2024)

· The relevant copyright clearance code notice is to be added at the bottom of the first page.

· For papers in which all authors are employed by the US government, the copyright notice is:

U.S. Government work not protected by U.S. copyright

· For papers in which all authors are employed by a Crown government (UK, Canada, and Australia), the copyright notice is:

· For papers in which all authors are employed by the European Union, the copyright notice is:

· For all other papers the copyright notice is:

Step-3 IEEE Xplore-compatible PDF generation and upload

· The Final camera-ready manuscript must be converted into PDF with settings compliant with the requirements of the IEEE Xplore digital library. Use IEEE PDF eXpress tools to check for PDF compatibility.

· The PDF eXpress site can be accessed here, the Conference ID is 64447X.

First-time users of IEEE PDF eXpress should do the following:

1. Click on create account

2. Enter the following:

· 64447X for the Conference ID

· your email address

· a password

3. Continue to enter information as prompted.

4. An online confirmation will be displayed and an email confirmation

will be sent.

5. Verify your account setup.

· Once the paper has been checked (you will be notified by an email), please access again PDF eXpress and click on the “Approve” icon on the right side in the “Action” column.

· Be careful: without clicking on “Approve”, you may not receive your PDF file.

· If you are having problems using PDF Express, please contact the Publication Chairs.

Existing users of IEEE PDF eXpress

Existing users of PDF Xpress need to follow the above steps, but should enter the same password that was used for previous conferences. Verify that your contact information is valid.

Submit your final Camera-Ready paper to https://cmt3.research.microsoft.com/ATS2024/Submission/Index

Step 4: IEEE electronic copyright form submission

· Login into CMT and prompt to Author console.

· By clicking on the ‘Submit IEEE copyright form’ link in the Author Console, authors will be redirected to the IEEE eCF site to submit the copyright form. After filling out the IEEE copyright form on eCF site, Authors need to download the form and upload it on CMT.

Paper without completed copyright form will not appear on the conference proceedings and will not be published in IEEE Xplore.

For presentation at conference, please use ATS 2024 presentation template available here

List of Accepted Papers

Paper ID	Paper Title
Full Paper ( Paper Length: 6 pages, Presentation time: 30 mins) (Total:32)
16	Trojan Horse Detection for RISC-V Cores Using Cross-Auditing
30	An FPGA-Based Emulation Platform for Functional Safety Verification in Automotive SoC Systems
32	Effective Runtime Fault Detection for DNN Accelerators
34	Reliability Enhancement of Memristor-Based Neural Networks with Fault-Injected Training
42	A Formal Approach and Testing Process for Failure Modes in Intelligent Algorithms
47	Boosting self-repair workflow with brainstorming for code generation
51	Low-cost generation of RF test stimuli from baseband digital signals
52	A Novel Multi-Scope Characterization Method for Automotive LPDDR4 Controller
53	Automotive Microcontroller Characterization Hardware – Challenges and Solutions
56	High performance advanced fault model diagnosis
58	Carbon Quantum Dot Fluorescent Stickers for Biochip Authentication
61	Hacking the Fabric: Targeting Partial Reconfiguration for Fault Injection in FPGA Fabrics
71	Fault Tolerance in Stochastic Circuits for Recurrent Sequential Neural Networks
72	Optimized Detection of Marginal Defects Using Unsupervised Learning
77	A Complete Security Protocol To Safeguard IJTAG Architecture
80	Automated System for Testing and Result Analysis for Payload Controller
87	A Novel TSV Repair Framework for 3-D Stacked ICs
90	SAMURAI: Safeguarding against Malicious Usage and Resilience of AI
91	LATENT: Leveraging Automated Test Pattern Generation for Hardware Trojan Detection
93	FORTUNE: A Negative Memory Overhead Hardware-Agnostic Fault TOleRance TechniqUe in DNNs
95	PATROL: An Evolutionary Approach to Automatic Test Pattern Generation for Hardware Trojan Detection Leveraging PSO-GA Hybrid Techniques
124	A Testability Improvement Method of Combinational Circuits Based on the SDC Conditions
145	A Novel Differential 12T SRAM Bit-cell Structure with Improved SNM in 16nm FinFET Technology
147	Testing Method for Embedded UltraRAM in Field Programmable Gate Arrays
157	Design, Implementation and Characterization of a Novel Robust-by-Construction Arbiter PUF Circuit on Xilinx FPGAs
163	MEMFD: A Multi-EDT Multi-Fault Scan Chain Diagnosis Methodology with Deep Learning
164	SFCM-HT: Hardware Trojan Detection Based on Sequence Features with a Combination Model
168	Accelerating Sequential Circuit Simulation with Spatial Locality Enhancement and Redundant Event Reduction
174	LLM-aided Front-End Design Framework For Early Development of Verified RTLs
175	ML Based Diagnosis for Fault Location in Digital Circuits
181	Evaluating Different Fault Injection Abstractions on the Assessment of DNN SW Hardening Strategies
Short Paper ( paper length: 4-pages, Presentation time : 20 mins)
14	MTCX：Ultra-high Throughput TRNG Based on Mesh topology of coupled-XOR
36	Methods and Apparatus to Support Multiple Synchronous Clocks with a Single Clock Mesh
68	Post-silicon Trace Signal Selection Using Genetic Algorithm
70	Preferential Fault-Tolerant based TF32 Floating Point Adder for Mission Critical Systems
73	Power Aware test methodology for Test Power hungry complex SoCs
74	Optimizing LBIST Run Time for a Safety Critical SoC: A Practical Approach
82	Large Language Model Driven Logic Locking: A Generative Approach to Secure IC Design
98	Design and Simulation of Fault Detection Technique for NAND Based Memory Array
132	RTL design of 16-bit RISC Processor Using Vedic Mathematics
135	Improving At-Speed Test Coverage without compromising Test Time and reducing Test Cost in multi-partition SCAN Design
140	Novel Single Ended Read and Differential Write Secure SRAM Memory Design Using Half Supply Voltage Precharge Approach
143	Enhancing SRAM Array Security Through Transmission Gate-Based Logic Obfuscation
SS1: Security and Test in Artificial Intelligence (Session Chair-Prof Rahaman and Prof Chandan Giri)
	Security Vulnerabilities in AI Hardware: Threats and Countermeasures
	Secure AI Systems: Emerging Threats and Defense Mechanisms
221	Security Concerns of Machine Learning Hardware
	Fault Testing in AI-Accelerators: A Review
SS2-Next-Gen EDA: Integrating LLMs for Enhanced Electronic Design (Session Chair – Prof Anupam Chattopadhyay)
219	RTL Agent: An Agent-Based Approach for Functionally Correct HDL Generation via LLMs
220	LLMs for Hardware Verification: Frameworks, Techniques, and Future Directions
222	LLM vs HLS for RTL Code Generation: Friend or Foe?
SS3-Quantum Technology ( Session Chair- Dr Kunal Korgaonkar)
223	Research frontiers in Quantum Technologies: Perspectives from the Indian Context
224	Finite element analysis (FEA) based design optimization of ultrastable, high finesse optical cavities for portable optical atomic clock applications
225	Quantum Computing for Medical Diagnosis: From Qubits to Cures
226	Experimental Realization of Quantum Memory and EPS-QKD
230	Quantum Key Distribution-Based Framework for Securing Encrypted Communications in Address Resolution Protocol Packet Capture
SS4-In Memory Computing (session chair – Prof Indranil Sengupta)
169	Improving Self-Fault-Tolerance Capability of Memristor Crossbar Using a Weight-Sharing Approach
189	Towards Formal Verification for MAC-based In-Memory Computing
Industry Session- 1 (Session Chairs: Prachi Patel Cadence, Nirav Nanavati-eInfochips, Jay shah-Alphawave)
38	Planning Ahead For End-to-end Formal Complexity
111	Enhancing Test Quality by Targeting Zero DPPM using Physical Defect based ATPG
121	Framework for Resolving Dependencies between Testbenches in Analog Circuit Simulation
184	Resolving Silicon Flaws in Multi-Bit Register Layouts and Yield Analysis A Compilation of Case Studies.