TTTC Workshop on “VLSI Test and Reliability”

The Department of Electronics and Communication Engineering organized a three-day (Test Technology Technical Council) Workshop on VLSI Test and Reliability for the students as well as the professionals during 2-4 March 2023. The Workshop was coordinated by Dr Usha Mehta, Head of Electronics and Communication Engineering Department & PG coordinator (VLSI Design) and Dr Vaishali Dhare, Assistant Professor, Electronics and Communication Engineering Department. Total 109 participants including ISRO professionals, PhD scholars, faculty members, PG students and UG students took part in this Workshop.

The detailed schedule is as follows:

The event began on 2nd March, 2023 at 9:30am by welcoming the dignitaries, lighting the lamp and brief introductory address about the workshop by HOD, EC Dr Usha Mehta. Chief Guest Dr. R. N. Patel, Director, ITNU, addressed the participants and presented memento to the dignitaries. Inaugural ceremony was concluded by giving a vote of thanks followed by the National Anthem.

2nd March 2023, Thursday: 

Session 1: Introduction to Design for Test by Mr. Prasad Mantri,

Mr. Prasad Mantri is the Chief Technology Officer from AISemicon. In this session, Mr. Prasad Mantri talked about TTTC and various international conferences for testing. He also talked about various standards for testing. He also briefed about ITC test India.

Session 2: Scan Based Testing by Mr. Vishal Diwan

Mr. Vishal Diwan is Digital Design Manager in Texas Instruments. He explained the basic DFT architecture, scan flip flops, scan chain, and scan chain reordering. He also explained LOC vs LOS used in testing. He explained scan design with the help of Timing diagram.

Session 3: Scan Compression by Mr. Rajit Karmakar

Mr. Rajit Karmakar is DFT CAD Engineer at Intel. In this session, he explained how a single scan chain can be formed into multiple scan chains. He gave an understanding of test compression and dictionary-based code. Participants also learnt various compression circuits and LFSR based test compression.

Session 4: Logic BIST by Mr. Malav Shah

Mr. Malav Shah is SoC Design Manager at Texas Instruments. It was one of the best sessions. He gave a quick recap of the whole DFT and explained real life testing in the field. He also motivated participants for Logic BIST. Participants also got to know various defects, bugs and a method to form test patterns for it.

Participants were very curious about testing and asked many questions. The speakers answered to all the questions asked by B. Tech students, as well as all the higher level real life challenges faced by ISRO professionals.

3rd March 2023, Friday: 

Session 5: Test Standards by Mr. Prasad Mantri

In this Session, Mr. Prasad Mantri talked about the need for test standards. He explained what is 1149.1 standard and what is JTAG standard, and why they are used for testing. He also explained the architecture of JTAG and explained what is BSDL.

Session 6: Memory Testing by Mr. Rajit Karmakar

In this session, Mr. Rajit Karmakar explained the 6T CMOS based memory cell and DRAM cells. He explained about the memory BIST. He also explained what is MARCH test and why it is the best for memory and explained about checkboard algorithm.

Session 7: Advance Fault models by Mr. Vishal Diwan

In this session, Mr. Vishal Diwan talked about various fault models in DFT. He explained what is SAF, TDF, PDF, BDF, SDD, CAF. He also explained about hold time test and RAM sequential testing.

Session 8: Test Diagnosis by Mr. Bharath Nandkumar

Mr. Bharath Nandkumar is Principal Software Engineer at Cadence. In this session, he talked about why we need diagnosis and what is logic diagnosis. He explained scan chain diagnosis and discussed various stuck at fault issues. He also explained fault simulation and some advanced diagnosis technique.

4th March 2023, Saturday: 

Session 9: DFT as a Career by Mr. Prasad Mantri

In this Session, Mr. Prasad Mantri talked about AI/ML requirement in edge system, SSN, TPI and some new fault models. He also explained design for quality as time to profitability is very large in semicon market. He also discussed how appetite to survive is required in start-ups.

All the participants attended the sessions enthusiastically, and the session ended with interaction and discussions with the speakers. All the participants and the speakers shared their views about the workshop.

The Lab session began from 10:00 am onwards. There were 40 working computers with cadence license in VLSI lab and Embedded lab. Participants were distributed in these two labs where the experts explained the flow of genus for DFT insertion. In the next lab session, they explained the Modus flow for ATPG and Diagnosis for 256-bit counter design.

The active participation of the students and professionals, insightful questions, and valuable contributions were the key factors that made the workshop a success. The event was concluded at 5:00 pm. Dr Usha Mehta, Coordinator, HoD, EC Department expressed a heartfelt thanks to everyone who participated in the workshop. The vote of thanks was presented to the workshop speakers who shared their knowledge and experiences with us. Their expertise and dedication were truly inspiring. They also acknowledged the efforts of the organizing committee and volunteers who worked tirelessly to ensure that the workshop was conducted smoothly.