A two days workshop on ?RISC-V Boot Camp? was organised by Electronics and Communication Engineering Department jointly with SiFive during March 2-3, 2020. The workshop was conducted by SiFive officials and coordinated by Dr Usha Mehta, Professor, Department of Electronics and Communication Engineering, Institute of Technology. SiFive is the first fabless semiconductor company to build customised silicon based on the free and open RISC-V instruction set architecture. The workshop was aimed for the faculty members, research scholars, Industries and R&D personals. It included key concepts of the open RISC-V instruction set architecture and hands-on FPGA development board. More than 150 participants have attended this workshop.
The workshop was inaugurated with a keynote address by Dr Krste Asanovi?, Chief Architect and the Co-Founder of SiFive through video lecture. He briefed the audience on the journey towards RISC?V foundation and its impact on upcoming future technology. Further insight on RISC?V was given by Mr. Anand Baria, Vice President, SiFive. He introduced the current application of RISC-V in the industry and the role of SiFive in making RISC-V related products.
Mr Rajesh Varadharajan, Director, IP Engineering, SiFive discussed the different architecture of RISC V. He briefed the audience about the bus architecture used for the RISC-V and its usage with other protocols like AMBA bus architecture. He also demonstrated the design flow of SciFive studio and the configuration of available RISC-V cores.
On the second day of the programme, Mr Rajesh Varadharajan conducted a hands-on session. The participants were given a development board with debuggers in a group of six persons by SiFive officials. Hands-on ARTY ?A7 tiny board with Linux SciFIve Studio was carried out to create the RISC-V with the SciFive IDE environment. Few experiments were carried out on that board by participants under the guidance of SiFive team.