Tutorial Topic: RAM-Sequential Test – Enabling Ultra-Low DPPM for Safety Critical Automotive Devices

 

Speakers:

1.      Mr. Prabhans Tiwari, Texas Instruments

2.      Mr. Vishal Diwan, Texas Instruments

 

About: With rapid growth in integration of multiple functions into SoCs, the huge requirement for on-chip data processing and storage has caused a steep increase in number of memories used per design. Hence in present age designs, on-chip memories are observed to have the dominant footprint contributing to significant percentage of total chip area. It has been observed that these memory functional interface paths are the top critical paths in the design. This in turn has created a greater emphasis on effective testing of these memories in order to achieve near zero DPPM for safety critical designs. In this section, we will discuss the need of RAM-sequential tests in emerging semiconductor technologies and how RAM-sequential tests capture unique defects missed by the traditional and other advanced fault models.

 

Working professional with DFT/test background and anyone from academia will benefit from this tutorial. Basic understanding of scan-based test would be helpful in better understanding of this tutorial.

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Tutorial Topic: Methods for Security-Aware Testing of 2.5D/3D HI Systems

 

Speakers:

1.      Jonti Talukdar- NVIDIA, Santa Clara

2.      Prof. Krishnendu Chakrabarty – Arizona State University USA

 

About: Recent breakthroughs in heterogeneous integration (HI) technologies using 2.5D and 3D ICs have led to significant advances in the semiconductor fabrication industry, enabling the design and development of disaggregated systems through

stacked multi-die packages. HI systems provide several benefits including higher density/performance at reduced power consumption, lower development costs and diminished time-to-market. However, HI technology has also led to several sources of distrust due to the use of third-party (untrusted) IP, outsourced assembly, testing, and fabrication facilities in the design and manufacturing process. Furthermore, the globalization of the integrated circuit (IC) supply chain poses significant risk to the security of intellectual property (IP) used in the design and development of 2.5D/3D HI systems. Testing of 2.5D/3D HI systems also remains challenging under the rapidly evolving threat landscape in an untrusted globalized supply chain, acting as a key attack surface for information leakage and system-level reverse engineering.

 

The tutorial will benefit audiences who are interested in learning about 3D/2.5D Test of HI systems, hardware security and trust for HI systems, security analysis for 3D/2.5D test interfaces, and side-channel analysis. The tutorial will start with basic concepts of testing and security for 2D circuits and build up to advanced methods for securing 3D/2.5D test interfaces. Audiences with basic understanding of testing and security principles should be able to attend this session. Audiences will also get exposed to the latest state-of-the-art practices for security analysis of 2.5D/3D HI systems through this tutorial.

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Tutorial Topic: At-Speed Test Methods for Complex Synchronous ASICs and Test Challenges, Practical Solutions  

 

Speakers:

1.      Veerabhadrarao Vasa – Google 

About: DFT architectural technique that enables scalable, independent, modular test development and test application for embedded design blocks & Test of logic around these blocks. Core is the lowest hierarchical level where patterns can be generated & applied.

 

A Standard wrapper structure, consisting of wrapper cells(WC) was added around the core boundary, Called Core Wrapper Chain(CWC), helps to target logic internal to core and external to core.

 

Helpful to partition large designs into smaller blocks of more manageable size and to facilitate test reuse more often at the level of physical implementation levels. Manageable ATPG & Simulation Runtimes, More Flexibility. Core Wrapping method is agnostic to functionality of design, enables the re-use of vectors. Blocks Xs from IP boundaries.

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Tutorial Topic: Memory Testing in Sub Nanometre Technologies: Challenges and Solutions  

 

Speakers:

1.      Sanjith Sleeba, Qualcomm

2.      Rahul Sahu, Qualcomm

3.      Subhadip Kundu, Qualcomm

       About: SRAM’s now occupy 40-60% of die area for SOC & ASIC in sub nanometre designs. At the same time, the SRAM design has become complex and feature sizes have shrunk with each generation of manufacturing technology. This has made the ATE test, reliability, diagnosability and yield as major challenges for high volume manufacturing. Problems of yield overkills, escapes of subtle defects, thermal runaways during test, field failures are increasingly seen by the memory test engineers.

In this tutorial, we will give an industrial perspective to these problems and the common methods used to solve them. The Tutorial will give an overview of the SRAM design and the challenges it poses for design and test. The MBIST (Memory Built-In Self-Test) hardware design and memory test algorithms will be described, along with their deployment in post silicon test to catch time zero failures and potential yield and reliability deterrents. The Tutorial is meant to equip the memory test engineers with the know-how needed to address the issues seen in advanced technology nodes.

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Tutorial Topic: Linking Physical Defects, Fault Models and Silicon Failures  

 

Speakers:

1.      Kamlesh Pandey, Krivya Semicon Pvt Ltd

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Tutorial Topic: Stuck-at Fault Model: Its Justification

 

Speakers:

1.      Prof Janak Patel- University of Illinois, USA

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