Call for Tutorial

The 33rd IEEE Asian Test Symposium (ATS) will be held from 17th December to 20th December, 2024, at Ahmedabad, Gujarat, India. ATS 2024 provides an international forum for engineers and researchers to present and discuss various aspects of device, board, and system testing -covering the complete cycle from design verification, design-for-test, design-for-manufacturing, silicon debug, manufacturing test, system test, diagnosis, reliability and failure analysis, and back to process for design improvement. We invite proposals for Tutorials to be presented at ATS 2024. Tutorials aim to provide the test community with a comprehensive treatment of timely topics of interest. Topics related to design and test development across multi geographical regions will be of special interest. Authors are invited to submit original, high quality, practical and industry best practices as Tutorials describing recent work in the field of test and design.

Conference Website: https://ec.nirmauni.ac.in/ats-2024/
History of ATS: http://www.ieee-ats.org/
Connect with ATS: https://www.linkedin.com/company/ats-2024

Contributions are invited in the following areas:

  • 3D/2.5D Test
  • Adaptive Test in Practice
  • ATE/Probe Card Design
  • Automotive
  • A.I.
  • Advances in Boundary Scan
  • Silicon Bring Up
  • Data Driven Methods
  • Data Exchange and Infrastructure
  • Defect-Oriented Testing
  • DFM and Test Diagnosis
  • Economics of Test
  • End-to-End Data Analysis
  • Embedded BIST & DFT
  • Emerging Defect Mechanisms
  • Hardware Security and Trust
  • IoT Testing
  • Known-Good-Die testing
  • Memory Test and Repair
  • MEMS Testing
  • Mixed-Signal and Analog Test
  • New Technologies and Test
  • On-Chip Test Compression
  • Online Test
  • Pre- and Post- Silicon Validation
  • Power Issues in Test
  • Protocol-aware Test
  • Reliability and Resilience
  • Scan Based Test
  • Security
  • SoC/SiP/NoC Test
  • Silicon Debug
  • Jitter, High-Speed I/O and RF Test
  • Simulation and Test
  • System Test (Applications)
  • System Test (Hardware/Software)
  • Test-to-Design Feedback
  • Test Escape Analysis
  • Test Flow Optimizations
  • Test Generation and Validation
  • Test Resource Partitioning
  • Test Standards
  • Test Time Analysis and Reduction
  • Testing High Speed Optics/Photonic
  • Yield Analysis and Optimization
Proposal Submission Deadline
Acceptance Notification Final Manuscripts Due
Date of Tutorial

: August 31, 2024
: September 30, 2024
: October 15, 2024
: December 17, 2024

Submission Guidelines

  • Tutorial title.
  • An electronic copy of a Tutorial program with a list of topics covered a short description of each topic and the approximate time devoted to each topic (about 2000 words).

Submission link: https://cmt3.research.microsoft.com/ATS2024/Submission/Index

  • Rationale for the session, emphasizing its importance and relevance to the ATS community.
  • The targeted audience and prerequisites (about 50 words).
  • Tutorial duration: should be 3 hours (for full tutorials) or 1.5 hours (for short tutorials).
  • Name, affiliation, e-mail address of each speaker.
  • Proposals will undergo a panel review process.
  • All presenters listed in the tutorial proposal must be available for tutorial presentation.
  • Consent should be obtained from all the presenters and all organizations involved in presenting the material before making the tutorial proposal.

Contact Information

For further details, please contact Tutorial Chairs:

We look forward to your contributions to the success of ATS 2024!
For more information, please visit the ATS 2024 website.