Original papers on, but not limited to, the following areas are invited:
• Analog/Mixed-Signal Test
• Automatic Test Generation
• Board Test and Diagnosis
• Boundary Scan Test
• Built-In Self-Test (BIST)
• Defect-Based Test
• Delay and Performance Test
• Dependability and Functional Safety
• Design for Test (DFT)
• Diagnosis and Silicon Debug
• Economic of Test
• Failure Analysis
• Fault Modelling and Simulation
• Fault Tolerance
• GPU Test
• High-Speed I/O Test
• Low-Power IC Test
• Memory Test and Repair
• Test for MEMS and Microfluidic Systems
• Multi-/Many-core Processor Test
• Test for Nanoscale Devices and Emerging Technologies
• On-line Test
• Power/Thermal/Reliability Issues in Test
• Reconfigurable System Test
• Test for Biomedical Circuits and Systems
• RF Test
• Hardware-oriented Security and Trust
• Self-Repair
• Test for Sensors and IoT
• SiP, Stacked, 3D IC Test
• Standards in Test
• Machine Learning in Test
• Test Compression
• Test Quality
• Test Synthesis
• Validation and Verification
• Yield Analysis and Enhancement
• Test for Reversible and Quantum Circuits