Conference Schedule
Tutorials, 17th December, 2024, Tuesday at D- Block, Nirma University Campus , Ahmedabad | ||||
Time | Agenda | Mins | ||
08:00AM-09:00 AM | Registrations |
| ||
09:00AM-10:30AM | RAM-sequential test – Enabling ultra-low DPPM for safety critical automotive devices by Prabhans Tiwari and Vishal Diwan – Texas Instruments | Linking Physical Defects, Fault Models and Silicon Failures by Kamlesh Pandey – Krivya Semicon Pvt Ltd | Methods for Security-aware Testing of 2.5D/3D HI Systems by Jonti Talukdar- NVIDIA, Santa Clara and Prof. Krishnendu Chakrabarty – Arizona State University USA | 90 |
10:30AM-10:45AM | Tea Break | 15 | ||
10:45AM-12:15AM | At-Speed test methods for complex synchronous ASICs and Test Challenges, Practical Solutions by Veerabhadrarao Vasa – Google | Linking Physical Defects, Fault Models and Silicon Failures by Kamlesh Pandey – Krivya Semicon Pvt Ltd | Methods for Security-aware Testing of 2.5D/3D HI Systems by Jonti Talukdar- NVIDIA, Santa Clara and Prof. Krishnendu Chakrabarty – Arizona State University USA | 90 |
12:15PM-01:00PM | Lunch Break | 45 | ||
01:00PM-02:30PM | Memory testing in sub nanometer technologies: Challenges and Solutions by Sanjith Sleeba, Rahul Sahu and Subhadip Kundu- Qualcomm | Stuck-at Fault Model: Its Justification by Prof Janak Patel- University of Illinois, USA | DFT for Automotive ICs by Nilanjan and Lee Lee Harrison – Siemens | 90 |
02:30PM-02:45PM | Tea Break | 15 | ||
02:45PM-04:15 PM |
| Stuck-at Fault Model: Its Justification by Prof Janak Patel- University of Illinois, USA | DFT for Automotive ICs by Nilanjan and Lee Lee Harrison – Siemens | 90 |
Conference Venue: Hotel Courtyard Marriot, Sindhubhavan, Ahmedabad
|
|
Venue-Samaya (3rd Floor) |
Venue-Samaya Pre-function (3rd Floor) |
Venue-Candela (1st Floor) |
|
|
Time |
Agenda |
Mins |
||
|
18th December, 2024,
Wednesday |
||||
|
08:00AM-09:00AM |
Registrations |
60 |
||
|
09:00AM-10:15AM |
Inaugration and Welcome (Chief Guest
: Ms Mona Khandhar-Principal Secretary, Science and Technology, Government of
Gujarat , Guest of Honour: Shree K K Patel-Vice President of Nirma
University), Venue-Samaya (3rd Floor) |
75 |
||
|
10:15AM-11:00AM |
Keynote Speech- Prof Rolf Drechsler,
University of Bremen, Germany (Session
Chair: Sameer Chillerige) Venue-Samaya (3rd Floor) |
45 |
||
|
11:00AM-11:15AM |
Tea Break |
15 |
||
|
11:15AM-12:00AM |
Keynote Speech -Prof Krishnendu
Chakrabarthy, Arizona State University, USA ( Session Chair: Prof Ujjwal
Guin) Venue-Samaya (3rd Floor) |
45 |
||
|
12:00AM-12:45PM |
Keynote Speech- Smt Sunita Verma, MeitY (Session Chair: Mr
Nikhil Sudhakar) Venue-Samaya (3rd Floor) |
45 |
||
|
12:45PM-01:30PM |
Lunch Break and Steering Committee
Meeting (Meeting Venue-Samaya
Pre-function (3rd Floor)) |
45 |
||
|
01:30PM-02:15PM |
Keynote Speech- Mr Nilanjan
Mukherajee, Siemens |
45 |
||
|
02:15PM-03:00PM |
Fireside Chat by Dr Satya Gupta-VLSI Society of India and
Ms Chitra Hariharan-Renesas Electronics |
45 |
||
|
03:00PM-04:30PM |
Regular Session 1 (Session Chair:
Prof Debesh Das, Jadhavpur University) Venue-Candela (1st Floor) |
Regular Session 2 (Session Chair:
Prof Janak Patel, University of Illinois, USA) |
SS1-Next-Gen
EDA: Integrating LLMs for Enhanced Electronic Design (Session Chair :
Prof Bhargab Bhattacharya, ISI
Kolkata ) Venue-Samaya Pre-function
(3rd Floor) |
90 |
|
Paper-id:61 Hacking the Fabric:
Targeting Partial Reconfiguration for Fault Injection in FPGA Fabrics
(Krishnendu Chakraborty, ASU) |
Paper-id:71 Fault Tolerance in
Stochastic Circuits for Recurrent Sequential Neural Networks (Roshwin
Sengupta, University of Stuttgart) |
Paper-id:
219 RTL Agent: An Agent-Based Approach for Functionally Correct HDL
Generation via LLMs (Prof Anupam Chattopdhyay, NTU Singapore) |
||
|
Paper-id:32 Effective Runtime Fault
Detection for DNN Accelerators (Prof Krishnendu, ASU) |
Paper-id:56 High performance advanced
fault model diagnosis (Bharath Nandakumar, Cadence) |
Paper-id:
220 LLMs for Hardware Verification: Frameworks, Techniques, and Future
Directions (Chandan Kumar Jha , University of Bremen) |
||
|
Paper-id:72 Optimized Detection of
Marginal Defects Using Unsupervised Learning (Karthik Pandaram, University of
Stuttgart) |
Paper-id:58 Carbon Quantum Dot
Fluorescent Stickers for Biochip Authentication (Navjit Singh, New York
University) |
Paper-id: 222 LLM vs HLS for RTL Code
Generation: Friend or Foe? (Chandan Karfa, IIT Guwahati) |
||
|
|
LLMs for
Verilog Code Generation ( Jeyavijayan Rajendran) |
|
||
|
04:30PM-04.45PM |
Tea Break |
15 |
||
|
04:45AM-05:00AM |
Felicitation Program |
15 |
||
|
05:00PM-06:00PM |
Industry Session -1 The latest trends
in 3D and 2.5D IC Testing (Session Chair- Kamlesh Pandey, Krivya
Semiconductor Pvt. Ltd) |
Regular Session 3 (Session Chair:
Prof Hafizur Rahaman, IIEST Shibpur ) |
Industry Session- 2 (Session Chair:
Ms Prachi Patel, Cadence Design Centre, Ahmedabad) |
60 |
|
IS11: Heterogeneous chiplet
integration and test challenges (Lee Harrison, Siemens) |
Paper-id:145 A Novel Differential 12T
SRAM Bit-cell Structure with Improved SNM in 16nm FinFET Technology (Ramesh
Devani, Microcircuits Technology) |
Paper-id:38 Planning Ahead For
End-to-end Formal Complexity (Shubhangi Goel, Marvell Semiconductor) |
||
|
IS12: 3D IC implementation and
interconnect test based on IEEE 1838 (Sameer Chillarige, Cadence) |
Paper-id:80 Automated System for
Testing and Result Analysis for Payload Controller (Anirban Paul, Space
Applications Centre) |
Paper-id:184 Resolving Silicon Flaws
in Multi-Bit Register Layouts and Yield Analysis A Compilation of Case
Studies. (Madhu Sai Krishna Kandrakota , Infineon) |
||
|
IS13: Multi-die (3D-IC) testability
challenges and solutions (Faisal Goriawalla, Synopsys) |
||||
|
06:00PM-06:15PM |
Break |
|
||
|
06:15-07:15PM |
Industry Panel Discussion on
“Semiconductor Design & Manufacturing – Insights and
opportunities” (H S Jatana-Former Group Head – Design & Process Grp.
SCL, Himanshu Soni-Director SoT Nirma University, Manish
Gurwani-IAS-MD-Gujarat State Electronics/Biotech Mission, Navin
Bishnoi-Country Head -Marvell India, Nilesh Ranpura-Director of Engineering
Arrow Inc. (einfochips), Sudhir Naik-Founder Member eInfochips, Sumit
Goswami-Senior Director Of Engineering, Qualcomm) |
|
||
|
07:15PM Onwards |
Dinner for invited guests |
|
||
|
19th December, 2024,
Thursday |
||||
|
08:00AM-09:00AM |
Registrations |
45 |
||
|
09:00AM-09:15AM |
Day1 Summary and Day 2 Welcome |
15 |
||
|
09:15AM-10:00AM |
Keynote Speech- Prof Kaushik Roy,
Purdue University, USA (Session Chair – Prof Sivanantham, VIT) |
45 |
||
|
10:00AM-10:45AM |
Keynote Speech – Dr Yervant Zorian,
President of Synopsys Armenia (Session Chair: Prof Ilia Polian) |
45 |
||
|
10:45AM-11:00AM |
Tea Break |
15 |
||
|
11:00AM-01:00PM |
SS2-In Memory Computing (session Chair:
Prof Indranil Sengupta) |
SS3-Security and Test in Artificial
Intelligence (Session Chair: Prof Chandan Giri) Venue-Samaya (3rd Floor) |
SS4-Quantum
Technology (Session Chair: Dr Kunal Korgaonkar) |
120 |
|
Keynote Speech on The Future of
Hardware Technologies for Computing by Prof Subhasish Mitra, Stanford
University |
Paper-id:234 Security Vulnerabilities
in AI Hardware: Threats and Countermeasures (Rajat Subhra Chakraborty, IIT
Kharagpur) |
Paper-id:224
Finite element analysis (FEA) based design optimization of ultrastable, high
finesse optical cavities for portable optical atomic clock applications
(Himanshu Miriyala, IIT Tirupati) |
||
|
Expert Talk on Real Digital
Processing-in-Memory by Prof. Shahar Kvatinsky, Technion, Israel Institute of
Technology |
Paper-id: 239 Secure AI Systems:
Emerging Threats and Defense Mechanisms (Habibur Rahaman,University of
FLorida ) |
Paper-id:226
Experimental Realization of Quantum Memory and EPS-QKD (Kapil Jaiswal,
Devendra Mishra, Quantum AI Global) |
||
|
Paper-id:189 Towards Formal
Verification for MAC-based In-Memory |
Paper-id: 221 Security Concerns of
Machine Learning Hardware (Nilotpola Sarma, IIT Guwahati) |
Paper id:230
Quantum Key Distribution-Based Framework for Securing Encrypted
Communications in Address Resolution Protocol Packet Capture (Gayathri M, SRM
Uni.) |
||
|
Paper-id: 169 Improving
Self-Fault-Tolerance Capability of Memristor |
Paper-id: 242 Fault Testing in
AI-Accelerators: A Review ( Hafizur Rahaman, IIEST, Kolkata, Debesh Kunar
Das, Jadavpur University) |
|
||
|
01:00PM-02:00PM |
Lunch Break |
60 |
||
|
02:00PM-04:00PM |
Regular Session 4 (Session Chair:
Prof Anupam Chattopadhyay, NTU, Singapore) |
Regular Session 5 (session Chair:
Bharath Nandakumar, Cadence) |
Regular Session 6 (Session Chair:
Malav Shah, Texas Instruments) |
120 |
|
Paper-id:90 SAMURAI: Safeguarding
against Malicious Usage and Resilience of AI (Habibur Rahaman, University of
Florida) |
Paper-id:87 A Novel TSV Repair
Framework for 3-D Stacked Ics (Tanusree Kaibartta, IITISM Dhanbad) |
Paper-id:47 Boosting self-repair
workflow with brainstorming for code generation (Zhaoming Jin, University of
Chinese Academy of Sciences) |
||
|
Paper-id:175 ML Based Diagnosis for
Fault Location in Digital Circuits (Subhajit Chatterjee, IIEST – Shibpur) |
Paper-id:91 LATENT: Leveraging
Automated Test Pattern Generation for Hardware Trojan Detection (Sudipta
Paria , University of Florida) |
Paper-id:16 Trojan Horse Detection
for RISC-V Cores Using Cross-Auditing (Siang-Cheng, Huang, NTHU) |
||
|
Paper-id:181 Evaluating Different
Fault Injection Abstractions on the Assessment of DNN SW Hardening Strategies |
Paper-id:51 Low-cost generation of RF
test stimuli from baseband digital signals (Florence AZAIS, LIRMM, Univ.
Montpellier, CNRS) |
Paper-id:95 PATROL: An Evolutionary
Approach to Automatic Test Pattern Generation for Hardware Trojan Detection
Leveraging PSO-GA Hybrid Techniques (Ali Azarpeyvand, University of Zanjan)) |
||
|
Paper-id:174 LLM-aided Front-End
Design Framework for Early Development of Verified RTLs (Binod Kumar, IIT
Jodhpur) |
Paper-id:164 SFCM-HT: Hardware Trojan
Detection Based on Sequence Features with a Combination Model (Zhenghao Li,
National University of Defense Technology, China) |
Paper-id:93 FORTUNE: A Negative
Memory Overhead Hardware-Agnostic Fault TOleRance TechniqUe in DNNs (Mahdi
Taheri, Tallinn university of technology) |
||
|
04:00PM-04:15PM |
Tea Break |
15 |
||
|
04:15PM-05:45PM |
Regular sesiion 7 (Session Chair:
HariSankar Gupta) |
Short Paper 1 (Session Chair: Prof R
A Thakker) |
ATS Doctoral Thesis Award Contest
(Session Chair-Prof Indranil Sengupta) |
90 |
|
Paper-id:34 Reliability Enhancement
of Memristor-Based Neural Networks with Fault-Injected Training (Md. Sihabul
Islam, Nara Institute of Science and Technology, Japan) |
Paper-id:73 Power Aware test
methodology for Test Power hungry complex SoCs (Pervez Garg, Texas
Instruments) |
Thesis-id: T1 Test Data Compaction
Techniques with Improved Diagnostic Capabilities and Reduced Tester Time |
||
|
Paper-id:68 Post-silicon Trace Signal
Selection Using Genetic Algorithm (Hanxu Feng, Beijing Microelectronics
Technology Institute) |
Paper-id:36 Methods and Apparatus to
Support Multiple Synchronous Clocks with a Single Clock Mesh (Shubham
Shrivastava, Marvell India Pvt. Ltd.) |
Thesis-id: T2 Modeling and
Performance Improvement Techniques for GNR and CNT On-Chip Interconnect |
||
|
Paper-id:14 MTCX：Ultra-high
Throughput TRNG Based on Mesh topology of coupled-XOR (Liang Yao, Hefei
University of Technology) |
Paper-id:135 Improving At-Speed Test
Coverage without compromising Test Time and reducing Test Cost in
multi-partition SCAN Design (Jayesh Popat, Microcircuits Innovations Pvt Ltd) |
|
||
|
|
Paper-id:143 Enhancing SRAM Array
Security Through Transmission Gate-Based Logic Obfuscation (Bhavin Bhavani,
DAIICT, Gandhinagar) |
|
||
|
05:45PM onwards |
Cultural Evening and Gala Dinner |
|
||
|
20th December, 2024,
Friday |
||||
|
08:00AM-09:00AM |
Registrations |
15 |
||
|
09:00AM-09:15AM |
Day 2 Summary and Day 3 Welcome |
15 |
||
|
09:15AM-10:00AM |
Keynote Speech “Monolithic SOCs
and Chiplet Based Designs Present New Challenges in Test and
Reliability”- Dr Adit Singh, Auburn University (Session Chair: Prof Usha
Mehta) |
45 |
||
|
10:00AM-10:30AM |
Keynote Speech- Infineon (Session
Chair: Nikhil Sudhakar)) |
45 |
||
|
10:30AM-10:45AM |
Tea Break |
15 |
||
|
10:45AM-01:15PM |
Regular Session 8 (session Chair:
Nirav Nanavati) |
Short Paper 2 (session Chair: Mr
Chintan Panchal, eInfochips) |
Regular Session 9 (Session Chair: Mr
Nikhil Sudhakar) |
150 |
|
Paper-id:163 MEMFD: A Multi-EDT
Multi-Fault Scan Chain Diagnosis Methodology with Deep Learning (Binod Kumar,
IIT Jodhpur) |
Paper-id:82 Large Language Model
Driven Logic Locking: A Generative Approach to Secure IC Design (Jugal
Gandhi, CEERI, Pilani) |
Paper-id:124 A Testability
Improvement Method of Combinational Circuits Based on the SDC Conditions |
||
|
Paper-id:157 Design, Implementation
and Characterization of a Novel Robust-by-Construction Arbiter PUF Circuit on
Xilinx FPGAs (Balijabudda Venkata Sreekanth, IIT Kharagpur) |
Paper-id:70 Preferential
Fault-Tolerant based TF32 Floating Point Adder for Mission Critical Systems
(Sakali Raghavendra Kumar, S S Nadar College of Engineering, Kalavakkam,
Chennai) |
Paper-id:30 An FPGA-Based Emulation Platform for
Functional Safety Verification in Automotive SoC Systems (SUN YUTAO, Beijing
University of Posts and Telecommunications) |
||
|
Paper-id:53 Automotive
Microcontroller Characterization Hardware – Challenges and Solutions (Vasavi
Ghanta, Infineon) |
Paper-id:98 Design and Simulation of
Fault Detection Technique for NAND Based Memory Array (Jamuna S, Dayananda
Sagar College of Engineering) |
Paper-id:42 A Formal Approach and
Testing Process for Failure Modes in Intelligent Algorithms |
||
|
Paper-id:52 A Novel Multi-Scope
Characterization Method for Automotive LPDDR4 Controller (Vasavi Ghanta,
Infineon) |
Paper-id:132 RTL design of 16-bit
RISC Processor Using Vedic Mathematics (Madhura R, Dayananda Sagar College of
Engineering) |
Paper-id:168 Accelerating Sequential
Circuit Simulation with Spatial Locality Enhancement and Redundant Event
Reduction (Jiaping Tang, Chinese Academy of Sciences University of Chinese
Academy of Sciences) |
||
|
Paper-id:77 A Complete Security
Protocol To Safeguard IJTAG Architecture (K Sudeendra Kumar, PES UNIVERSITY,
BANGALORE) |
Paper-id:74 Optimizing LBIST Run Time
for a Safety Critical SoC: A Practical Approach (Sujeet Maurya, Texas
Instruments) |
Paper-id:147 Testing Method for
Embedded UltraRAM in Field Programmable Gate Arrays (Jiaqi Guo, Fudan
University) |
||
|
01:15AM-02:00PM |
Lunch Break |
45 |
||
|
02:00AM-03:00PM |
Vote of thanks, Doctoral Thesis winners,
Closing Ceremony |
30 |
||
|
3:30PM Onwards |
Goodbye Tea with networking
discussion followed by local sight seeing |
|
||